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    Test Number : HP2-E59
    Test Name : Introduction to Selling Servers Storage Networking and Services
    Vendor Name : HP
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    Introduction to Selling Servers Storage Networking and Services certification

    ARM challenging Intel in the Server Market: an overview | HP2-E59 Dumps and Real test Questions with VCE Practice Test

    "Intel doesn't have any competitors in any respect in the midrange and high-conclusion (x86) server market". They came to that somewhat boring conclusion in their review of the Xeon E5-2600 v2. That date turned into September 2013.

    at the identical time, the variety of announcements and press releases about ARM server SoCs according to the brand new ARMv8 ISA have been pretty much uncountable. AppliedMicro changed into asserting their sixty four-bit ARMv8 X-Gene again in late 2011. Calxeda despatched us a real ARM-based server at the end of 2012. Texas instruments, Cavium, AMD, Broadcom, and Qualcomm announced that they might be difficult Intel within the server market with ARM SoCs. these days, the first retail items have finally seemed in the HP Moonshot server.

    there has been no lack of muscular statements about the ARM Server SoCs. as an example, Andrew Feldman, the founding father of micro server pioneer Seamicro and the former head of the server branch at AMD cited: "within the historical past of computer systems, smaller, lessen-charge, and higher-extent CPUs have at all times received. ARM cores, with their low-vigor heritage in contraptions, may still enable energy-productive server chips." one of the most notorious silicon valley insiders even went so far as to say, "ARM servers are presently steamroller-ing Intel in key high margin areas however for some rationale the enterprise is pretending they don’t exist."

    leisure assured, they are able to not stop at opinions and press releases. As people begun speakme standards, they in fact got interested. let's examine how the Cavium Thunder-X, AppliedMicro X-Gene, Broadcom Vulcan, and AMD Opteron A1100 evaluate to the present and future Intel Server chips. we're working complicated to get all these contenders in their lab, and we're having some success, nonetheless it is simply too quickly for a full blown shoot out.

    Micro servers had been the primary the goal of the ARM licensees. customarily, a dialogue about Micro servers promptly turns right into a wimpy versus brawny core debate. one of the crucial factors for that is that Seamicro, the inventor of the micro server, first entered the market with Atom CPUs. The second intent is that Calxeda, the pioneer of ARM based servers, needed to work with the fact that the Cortex-A9 core was a wimpy core that could not contend with most server workloads. Wikipedia additionally buddies micro servers with very low vigour SoCs: “Very low vigor and small measurement server in line with gadget-on-Chip, usually established around ARM processor”.

    Micro servers are typically linked to low conclusion servers that serve static HTML, cache internet objects, and/or characteristic as gradual storage servers. it's authentic that you will not discover a 150W excessive-end Xeon interior a micro server, however that doesn't imply that micro servers are defined via low vigor SoCs. definitely, probably the most a hit micro servers are based on 15-45W Xeon E3s. Seamicro, the pioneer of micro servers, evidently indicated that there turned into little pastime in the low power Atom primarily based programs, however that sales spiked once they integrated Xeon E3s.

    presently micro servers are nevertheless a spot market. however micro servers are actually no longer hype; they are right here to reside, youngsters they don't consider they might be as dominant as rack servers and even blade servers in the near future. To have in mind why we'd make this kind of daring remark, it is important to keep in mind the precise explanation why micro servers exist.

    let us go returned to the past decade (2005-2010). Virtualization became (and is) embraced because the finest strategy to make corporations with many heterogeneous applications working on underutilized servers more efficient. RAM ability and core counts shot up. Networking and storage lagged however caught up – extra or less – as flash storage, 10 Gbit Ethernet, and SRIOV grew to be attainable. however the trend to observe changed into that virtualization made servers more I/O characteristic rich: the quantity and velocity of community NICs and PCI-e enlargement slots for storage multiplied straight away. Servers in response to the Xeon E5 and Opterons have turn into "application described datacenters in a box" with digital switching and storage. The leading driver for purchasing complicated servers with high processor counts and more I/O contraptions is primary: professionals want the merits that tremendously built-in virtualization application brings. quicker provisioning, excessive availability (HA), are living migration (vMotion), disaster recovery (DR), retaining historical services alive (working on windows 2000 for example): virtualization made every thing so tons more straightforward.

    but what in case you did not want these points because your utility is spread among many servers and might take a number of hardware outages? What in case you do not have the complex hardware sharing features reminiscent of SRIOV and VT-d? The prime illustration is an application like facebook, however rather a couple of smaller internet farms are in an analogous circumstance. if you do not have the aspects that include commercial enterprise virtualization application, you are just adding complexity and (consultancy/working towards) charges to your infrastructure.

    unluckily, as at all times, the trade analysts got here with unrealistic excessive predictions for the brand new micro server market: in 2016, they'd be 10% of the market, no less than "a 50 fold leap"! The simple fact is that there's lots of demand for "non-virtualized" servers, however they don't all should be as dense and low energy as the micro servers inside the Boston Viridis. The "very low power", extremely dense micro servers with their very low energy SoCs aren't a pretty good healthy for many workloads out there, aside from some storage and memcached machines. however there's a plenty greater market for servers denser than the existing rack servers, however much less complex and more cost-effective than the present blade servers, and there's a requirement for techniques with a relatively strong SoC, at present the SoCs with a TDP within the 20W-80W range.

    not satisfied? ARM and the ARM licensees are. the primary thing that Lakshmi Mandyam, the director of ARM servers methods at ARM, emphasised when they talked to her is that ARM servers may be focused on scale-out servers, now not just micro servers. The big difference is that micro servers are the usage of (very) low vigor CPUs, whereas scale-out servers are only servers that may run a lot and lots of threads in parallel.

    before they will focus on the ARM server SoCs, they want to study what they are up towards: the latest low end Xeons. we've described the midrange Xeon E5s in splendid element in prior articles.

    The Xeon E3-12xx v3 is nothing more than a Core i5/i7 "Haswell" dressed up as a server CPU: a quad-core die, 8MB L3 cache, and two DDR3 memory channels. You pay a small top class – a number of tens of bucks – for enabling ECC and VT-d guide. Motherboards for the Xeon E3 are additionally only just a few tens of greenback extra costly than a typical desktop board, and prices are between the LGA-1150 and LGA-2011 fanatic boards. The benefits are remote management courtesy of a BMC, mostly an Aspeed AST chip.

    For the fans which are due to the fact a Xeon E3, the server chip has additionally risks over or not it's computing device siblings. first of all, the boards consume somewhat a bit extra vigor whereas in sleep state: 4-6W instead of the average <1W of the computer boards. The rationale is that server boards come with a BMC and that these boards are alleged to be working 24/7 and not slumbering. So less time is invested in decreasing the vigor utilization in sleep mode: for instance the voltage regulators are chosen to are living long. additionally, these boards are tons greater choosy when it comes to DIMMs and expansions cards which means that clients should check the hardware compatibility lists for the motherboard itself.

    again to the server world, the main capabilities of the Xeon E3 is the only-threaded efficiency. The Xeon E3-1280 v3 runs the Haswell cores at three.6GHz base clock and may increase to 4GHz. There are also reasonably priced LP (Low vigour) 25W TDP models obtainable, e.g. the Xeon E3-1230L v3 (1.8GHz as much as 2.8GHz ) and E3-1240L v3 (2GHz as much as 3GHz). These chips seemed to be in very restricted deliver when they had been announced and had been very tough to locate remaining yr. happily, they have been obtainable in more suitable quantities due to the fact Q2 2014. It also price noting that the Xeon E3 wants a C220 chipset (C222/224/226) for SATA, USB, and Ethernet, which adds 0.7W (idle) to 4.1W (TDP).

    The vulnerable points are the limited memory channels (bandwidth), the indisputable fact that Xeon E3 server is proscribed to eight threads, and the very confined (for a server) 32GB RAM ability (four Slots x 8 DIMMs). clever memory or i am is among the companies it really is making an attempt to change this. alas their 16GB DIMMs will simplest work with the Atom C2000, resulting in the unusual circumstance that the Atom C2000 helps greater memory than the greater effective Xeon E3. they are going to show you their check results of what this capacity soon.

    The Atom C2000 is Intel's server SoC with a power envelope ranging from 6W (twin-core at 1.7GHz) to 20W (octal-core at 2.4GHz). USB 2.0, Ethernet, SATA3, SATA2 and the leisure (IO APIC, UART, LPC) are all integrated on the die, along side 4 pairs of Silvermont Cores sharing 1MB L2 cache. The Silvermont architecture should still procedure about 50% extra directions per clock cycle than previous Atoms due an stronger branch prediction, the loop stream detector (like the LSD in Sandy Bridge) and out-of-order execution. despite the fact the Atom micro structure remains a lot easier than Haswell.

    Silvermont has a whole lot smaller buffers (for example, the weight buffer only has 10 entries, the place Haswell has seventy two!), no memory disambiguation, it executes x86 directions (and never RISC-like micro-ops), and it may well technique on the most two integer and two floating factor instructions, with a optimum of two instructions per cycle sustained. The Haswell structure can system and sustain as much as five guidance with "ultimate" application. AES-NI and SSE four.2 instructions are available with the C2000, however AVX directions are not.

    The benefits of the Atom C2000 are the low vigor and high integration -- no further chip is required. The risks are the enormously low single-threaded efficiency and the fact that the vigor administration is not as superior because the Haswell architecture. Intel also wants some huge cash for this SoC: as much as $171 for the Atom C2750. The combination of an Atom C2000 and the FCBGA11 motherboard can at once surpass $300 which is fairly excessive compared to the Xeon E3.

    Calxeda, AppliedMicro and ARM – in that order – have been speaking about ARM based servers for years now. there were rumors about fb adopting ARM servers lower back in 2010.

    Calxeda become the primary to release a real server, the Boston Viridis, launched again in the beginning of 2013. The Calxeda ECX-one thousand was in response to a quad Cortex-A9 with 4MB L2. It turned into fairly sluggish in most workloads, nevertheless it changed into enormously energy effective. They discovered it to be a good CPU for low-end internet workloads. Intel's choice, the S1260, was in concept sooner, nevertheless it turned into outperformed in true server workloads through 20-forty% and crucial twice as tons power (15W versus eight.three W).

    lamentably, the single-threaded performance of the Cortex-A9 was too low. consequently, you essential fairly a little bit of costly hardware to compete with an easy twin socket low vigour Xeon running VMs. About 20 nodes (5 daughter playing cards) of micro servers or eighty cores have been indispensable to compete with two octal-core Xeons. The undeniable fact that they may use 24 nodes or 96 SoCs made the Calxeda primarily based server sooner, however the BOM (bill of substances) attached to so lots hardware became high.

    whereas the Calxeda ECX-a thousand might compete on performance/watt, it could not compete on performance per greenback. additionally, the 4GB RAM restrict per node made it unattractive for a few markets similar to internet caching. as a result, Calxeda become relegated to a number of area of interest markets such as the low conclusion storage market the place it had some success, but it was no longer sufficient. Calxeda ran out of undertaking capital, and a promising story ended too quickly, alas.

    AppliedMicro X-Gene

    only in the near past, AppliedMicro confirmed off their X-Gene ARM SoCs, but these are 40nm SoCs. The 28nm "ShadowCat" X-Gene 2 is due for the H1 of 2015. identical to Atom C2000, the AppliedMicro X-Gene ARM SoC has 4 pairs of cores that share an L2 cache. however, the similarity ends there. The core is lots beefier and it facets four-large difficulty with an execution backend with 4 integer pipelines and three FP pipelines (one 128-bit FP, one Load, one keep). the 2.4GHz octal-core X-Gene also has a decent 8MB L3 cache and might entry up to four reminiscence channels, with an built-in twin 10GB Ethernet interface. In different phrases, the X-Gene is made to head after the Xeon E3, now not the Atom C2000.

    Of route, the AppliedMicro chip has been delayed repeatedly. there were already performance bulletins in 2011. The X-Gene1 8-core at 3GHz was supposed to be a bit slower than a quad-core Xeon E3-1260L "Sandy Bridge" at 2.4GHz in SPECINT_Rate2006.

    because that the Haswell E3 is about 15-17% quicker clock for clock, performance may still be around Xeon E3-1240L V3 at 2GHz. however the X-Gene1 most effective reached 2.4GHz and never 3GHz, so it looks like an E3-1240L v3 will probably outperform the new challenger by means of a considerable margin. The E3-1230L (v1) was a 45W chip and the E3-1240L v3 is a 25W TDP chip, and as a result they also expect the performance/watt of an E3-1240L to be significantly enhanced. again in 2011, the SoC become anticipated to ship in late 2012 and have two years lead on the competitors. It grew to become out to be two months.

    simplest a thorough test like their Calxeda evaluate will in reality exhibit what the X-Gene can do, however is clear that AppliedMicro needs the X-Gene2 to be aggressive. If AppliedMicro executes smartly with X-Gene2, it could get forward as soon as again... this time confidently with a lead of more than two months.

    certainly, early next 12 months, things could get definitely interesting: the X-Gene2 will double to the amount of cores to sixteen (at 2.4GHz) or up the clock pace to 2.8GHz (eight-cores) courtesy of TSMC's 28nm method technology. The X-Gene2 is supposed to offer 50% more performance/watt with the identical volume of cores.

    AppliedMicro also introduced the Skylark structure inner X-Gene3. Courtesy of TSMC's 16nm node, the chip may still run at as much as 3GHz or have as much as 64 cores. The chip should still appear in 2016, but you'll forgive us for asserting that they first are looking to see and review the X-Gene2 earlier than they can be impressed with the X-Gene3 specs. we've considered too many companies with excessive numbers on PowerPoint presentations that don't pan out within the real world. then again, the X-Gene2 appears very promising and is already operating application. It just has to discover a spot in a true server in a well timed vogue.

    a couple of months ago, they talked briefly with the people of Cavium. Cavium is really expert in designing MIPS SoCs that enable clever networking, communications, storage, video, and safety purposes. The image below sums all of it up: current and future.

    Cavium's "Thunder assignment" begun from Cavium's existing Octeon III community SoC, the CN78xx. Cavium's bread and butter has been integrating excessive velocity network capabilities in SoCs, so you will be able to choose from SoCs which have a hundred Gbit Ethernet and 10GBit Ethernet. PCI-express roots and diverse SATA ports are all built-in. There is not any doubt that Cavium can design a enormously integrated feature-rich SoC, however what concerning the processing core?

    The MIPS cores inside the Octeon are lots less difficult – dual-challenge in-order – but additionally much smaller and wish very little power compared to a regular server core. 4 (28nm) MIPS cores can fit in the area of one (32nm) Sandy Bridge core.

    substitute the MIPS decoders with ARMv8 decoders and also you are almost there. although, while the Cavium Thunder-X is truly now not made to run SAP, server workloads are bit extra traumatic than network processing, so Cavium mandatory to enhance the Octeon cores. the brand new Thunder-X cores are still dual-concern, however they may be now out-of-order as a substitute of in-order, and the pipeline length has been increased from eight to 9 ranges to enable for larger clocks. each core has a 78KB L1 guideline cache and a 32KB records cache.

    The 37-manner 78KB L1 I cache is definitely strange, nonetheless it might possibly be more than just "network processor heritage". Their personal checking out and a couple of tutorial stories have shown that scale-out workloads such as memcached have a higher than general (that means the regular SPECIntRate2006 characterization) I-cache leave out expense. The reason is that these purposes run loads of kernel code, and extra primarily the code of the network stack. consequently, the application footprint is lots higher than expected.

    another reason why they accept as true with Cavium has finished it's homework is the incontrovertible fact that more die area is spent on cores (up to 48) than on large caches; an L3 cache is nowhere to be discovered. The Thunder-X has just one centralized relatively low latency 16MB L2 cache working at full core speed. loads of educational stories have validated that a big L3 cache is a waste of transistors for scale-out workloads. anyway essentially the most used guidelines that dwell in the I-cache, there's an immense quantity of much less often used kernel code that doesn't fit in an L3 cache. In other phrases, an L3 cache just provides greater latency to requests that neglected the L1 cache and in order to become within the DRAM anyway. that's also the explanation why Cavium made certain that a beefy reminiscence controller is accessible: the Thunder-X comes with 4 DDR3/4 seventy two-bit memory controllers and it at present supports the fastest DRAM available for servers: DDR4-2133.

    On the flip facet, having 48 cores with a relatively small 32KB D-cache that access one centralized 16MB L2 cache also ability that the Thunder-X is much less desirable for some "traditional" server workloads similar to SQL databases. So a Thunder-X core is simpler and possibly rather slightly weaker than an ARM Cortex-A57 in many ways, let alone an X-Gene core. The undeniable fact that the Thunder-X spends a whole lot much less transistors on cache than on cores certainly suggests that it is focused on other workloads. Single-threaded performance is probably going to be decrease than that of the AMD Seattle and X-Gene, nonetheless it could be shut ample: the Thunder-X will run at 2.5GHz, courtesy of global Foundries' 28nm manner know-how. Cavium is claiming that even the top SKU will maintain the TDP beneath 100W.

    there is greater. The Thunder-X uses Cavium's proprietary Coherent Processor Interconnect (CCPI) and can as a consequence work in a dual socket NUMA configuration. as a result, a Thunder-X based server can have as much as 96 cores and is able to assisting 1TB of reminiscence, 512GB per socket. assorted 10/40GBE, PCIe Root complex, and SATA controllers are built-in within the SoC. depending on SKU, TCP/IP Sec offload and SSL accelerators are additionally integrated.

    The accurate launch of Cavium's Thunder-X SKUs make it clear that Cavium is attempting to compete with the venerable Xeon E5 in some niche however huge markets:

  • ThunderX_CP: For cloud compute workloads similar to public and private clouds, web caching, net serving, search, and social media statistics analytics.
  • ThunderX_ST: For cloud storage, big information, and allotted databases.
  • TunderX_NT: For telecom/NFV server and embedded networking purposes.
  • ThunderX_SC: For comfy computing purposes
  • for the reason that Cavium's history and capabilities, it's relatively obvious that ThunderX_NT and SC should still be very equipped challengers to the Xeon E5 (and Xeon-D), however only a radical overview will tell how well the ThunderX_CP will do. one of the vital strongest facets of Calxeda turned into the tremendously integrated cloth that lowered the total vigour consumption and network latency of this type of server cluster. similar to AMD/Seamicro, Cavium is well located to make certain that the Thunder-X primarily based server clusters also have this high degree of community/compute integration.

    The 28nm octal-core AMD Opteron A1100 is much more modest and aims at the low end Xeon E3s. Stephen has described the chip in more element. To make sure a quick time to market, the AMD Opteron A1100 is made from existing constructing blocks already designed by means of ARM: the Cortex-A57 core and the Cache Coherent network or CCN.

    The AMD Opteron A1100 is without doubt one of the few vendors that makes use of the ARM interconnect. ARM put loads of work into this design to allow ARM licensees to build SoCs with loads of accelerators and cores. CCN is consequently a method of attaching all types of cores, processors, and co-processors ("accelerators") coherently to a quick crossbar, which also connects to four 64-bit reminiscence controllers, built-in NICs, and L3 cache. CCN is very comparable to the ring bus found interior all Xeon processors starting with "Sandy Bridge". The properly mannequin is the CCN-512 which supports as much as 12 clusters of quad-cores. This could influence in an SoC with 32 (8x4) A57 cores and 4 accelerators as an instance.

    AMD would now not inform us which CCN they are the usage of but they suspect that it's CCN-504. The rationale is this CCN turned into obtainable around the time work started on the Opteron A1100 and the indisputable fact that AMD mentions the ARM bus structure AMBA 5 of their slides. And it also makes feel: the CCN-504 supports as much as four x four cores and helps the Cortex-A57.

    It became rumored that the A1100 nevertheless used the CCI-400 interconnect, which is used through smartphone SoCs, however that interconnect uses the AMBA 4 structure. meanwhile the CCN-502 turned into introduced in October 2014, method too late to be inner the A1100.

    The AMD Opteron A1100 includes four pairs of "average" triple difficulty Cortex-A57 cores and 1MB L2 cache, with 8MB L3 cache.

    the important thing differentiator is the cryptographic processor that can accelerate RSA (relaxed Connection/hand shake) and AES (encrypting the information you ship and acquire) and SHA (a part of the authentication). Intel uses the PCIe short aid 89xx-SCC add-in card or the particular Intel communique chipset to supply a cryptographic coprocessor. These coprocessors are primarily used in professional firewalls/routers. as far as they comprehend such cryptographic processors are of restricted use in most https web services. Most modern x86 cores now guide AES-NI, and these guidance are well supported. in consequence, the present x86 CPUs from AMD and Intel outperform many co-processors when it involves precise world AES encoding/decoding of encrypted statistics streams.

    A cryptographic coprocessor may nonetheless be positive for the RSA asymmetric encrypted handshake, nevertheless it continues to be to be viewed if offloading the handshakes will in reality be quicker than letting the CPU deal with it, as each offload operation factors all types of overhead (such as a gadget call). A cryptographic coprocessor operating on the equal coherent community because the leading cores may be a lot more efficient than a PCIe equipment notwithstanding. It has loads of skills, however AMD couldn't supply us plenty info on the current state of software support.

    Broadcom is late to the sixty four-bit Server SoC birthday celebration, however the Broadcom Vulcan is likely one of the most bold designs.

    every core can have four threads in flight. Some could name it "tremendous-threading" or even "nice grained multi-threading" as only 1 thread is active in every cycle. The Vulcan core, impressed by using previous network processors, has four guide pointers (registers with the subsequent guideline handle) and 4 sets of architectural registers corresponding to the Oracle (in the past solar) Tx structure.

    despite the fact identical, the satisfactory grained multi-threading of the Vulcan seems tons greater advanced than the "Barrel-processor" method of solar's UltraSPARC T1 which cycled always between the four threads in flight. The thread scheduler seems to make a decision with some intelligence which thread it's going to fetch guidelines from in its place of simply cycling circular robin between threads.

    32 Bytes are fetched each and every cycle, first rate for eight instructions. The ARMv8 decoder is able to decoding 4 of these ARMv8A guidelines into four micro-ops. Six micro-ops can also be done per cycle: four integer and two floating element/NEON (128-bit) micro-ops.

    Broadcom guarantees that it'll offer ninety% of the performance of the Haswell Core. To reach 3GHz speed, Broadcom will use TSMC's 16nm FINFET know-how.

    Qualcomm, the business at the back of the massively a success "Krait" cell chips, has additionally introduced that it is going to enter the sixty four-bit ARM server SoC market. youngsters, Qualcomm has presented little else than the "conclusion of the x86 period, cloud alterations every little thing" shows that simplest make non-technical analysts excited, so they are expecting whatever greater immense.

    If it turned into any other business, they might have unnoticed the product as vaporware. but here is Qualcomm, the most a success ARM SoC company of the previous years. The current high-conclusion cellular chip, the 20nm Snapdragon 810 with four A57 core at 2GHz (and four A53) shows how smartly Qualcomm executes. Qualcomm has an staggering music record, so however they've yet to show anything tangible in the server area they are a drive to be reckoned with.

    Intel's response to all of those rivals is comparatively elementary. The Atom C2000 may not be effective enough to turn the ARM tide and the Xeon E3 may lose a efficiency per watt battle right here and there because of the extra PCH chip it needs. So take the two and unify the merits of the Xeon E3 and Atom C2000 in one chip, the Xeon-D. Then use Intel's main industry talents, essentially the most advanced process technology, in this case the 14nm 2nd technology of trigate transistors.

    The Xeon-D should still have all of it (practically): a Broadwell core that can go as low as 2W per core at 1.2GHz. it could also carry remarkable single-threaded performance if quintessential, as one core can go as high as 2.9GHz! Some individuals have noted that Intel may have a very hard time providing the same richness of integrated hardware blocks as the ARM licensees, but frankly the Xeon-D has well-nigh every thing a server software can need: several PCIe three.0 root advanced (24 lanes), 10GbE Ethernet, and PCH common sense (6x SATA, USB 3.0/2.0, eight lanes of PCIe 2.0 and 1GB Ethernet) are all built-in.

    Eight of those Broadwell cores will locate a spot in a 45W SoC. in view that Intel needs 6W to run two cores (and a small built-in GPU) at 1.4GHz, we'd not be shocked if the new Xeon-D might reach 1.8GHz or greater and that rapid enhance clocks should be above 3GHz.

    The handiest disadvantage that the SoC has in comparison to one of the crucial ARM SoCs is the dual-channel reminiscence controller. The Xeon-D could be attainable in Q3 2015. while roadmaps may still always be examine with warning, it need to be stated that Intel hardly delays its items more than just a few months. Intel has been executing very smartly, just about like clock work.

    Let's sum every little thing up in one huge table.

    ARM/Intel SoC 2015 assessment SoC Intel Xeon-D Intel Atom C2000 AppliedMicro X-Gene 1(X-Gene 2) AMD A1100 Cavium Thunder-X Broadcom Vulcan architecture Broadwell Silvermont Storm (ShadowCat) A57 Thunder-X Vulcan CoresSocket 8single 8single 8 (sixteen)sngle 4-8single 16-48dual 20? Max. CPU Clockspeed GHz 2.4GHz 2.4GHz(2.8GHz) 2GHz 2.5 Ghz 3GHz process eraIntel 14nm Intel 22nm TSMC 40nm(TSMC 28nm) GF 28nm GF 28nm TSMC 16nm L1 Cache 32KB I32KB D 32KB I24KB D 32KB I (*)32KB D (*) 48KB I32KB D 78KB I32KB D 32KB I32KB D Decode four 2 four three 2 four Max. IPC (int) five2 4 3 2 four Exe Ports 8 4 8 eight four? 6 Max. FP functionality2x 256 bit 1x 128 bit 2x 128 bit 2x 128 bit 2x 128 bit 2x 128 bit OoO buffer 192 32 >100 128 forty one hundred eighty L2 Cache 8x 256KB 4x 1MB 4x 256KB? (*) 4x 1MB 16MB 20x 256KB L3 Cache 8MB? - 8MB 8MB - ? Max. RAM 128GB 64GB 128GB 128GB 1TB ? memory Bus Width 2x 64-bit 2 x sixty four-bit 4x 64-bit 2x 64-bit 4x 64-bit 4x sixty four-bit DRAM (most desirable) DDR4-2133 DDR3-1600 DDR3-1866 DDR3-1866 DDR4-2133 DDR4-2133 TDP (precise SKU) 45W 20W 40W(25 W?) 25W +/- 95 W ? purchasable Q2-Q32015 Early2014 Now(Q2 2015?) Q1-Q22015 Q12015 Q32015

    (*) Deduced from Ganesh's article about the Helix SoCs

    These are paper specifications of direction, in order that they should still be interpreted with a grain of salt. It looks like the AMD A1100 should excellent the Atom C2000 and go after the low conclusion of the Xeon E3. AMD's Opteron A1100 is already available, however the latest development kits don't hit the clock pace and performance targets.

    The Thunder-X single-threaded efficiency in "traditional workloads" may only be at the level of the Atom C2000, however scale-out and community/crypto acceleration might deliver some marvelous results in certain workloads. The Cavium SoC is the hardest to predict and will exhibit a really variable efficiency profile as it also incorporates many very really expert hardware accelerators. The Thunder-X reference servers are introduced and will be accessible within the coming weeks.

    The X-Gene is currently the widest ARM structure with extra hardware acceleration basically focused on networking. The X-Gene TDP become first rate on paper (25W when announced) however there are lots of signs (40W TDP) that AppliedMicro definitely wants the 28nm X-Gene 2 to be in reality competitive within the performance/watt battle arena. The X-Gene 2 may still be obtainable around Q2 2015.

    the first SPECIntRate 2006 estimates have been published via "CPU meister" Andreas Stiller. If they combine his findings with what they comprehend and what is available at, they get the benchmark graph under.


    Intel's personal published SPECintrate ratings are up to 20% higher, so initially sight the ARM competition is not there yet. youngsters, they prefer to exhibit the "lower numbers" as they have not been benchmarked with masterfully set ICC configuration settings.

    probably the most aggressive architecture, the X-Gene, is quite slightly slower than the Xeon E3-1230L. The latter needs about 40W per node (SoC + chipset), while an X-Gene node would want essentially 60W. AppliedMicro really needs the 28nm 2.8GHz X-Gene 2, which curiously can offer a 50% more desirable efficiency per watt increase in SPECintrate 2006.

    however, they now have proven you that whereas SPECintrate 2006 is the usual commonly used, typical with most CPU designers, analysts and educational researchers, it is a gorgeous unhealthy predictor of server efficiency. They should still not bargain the possibilities of the server ARM SoCs too at once. A mediocre SPECint SoC can nevertheless operate neatly in server purposes.

    There isn't any doubt that purchasers would improvement from Intel being challenged within the server market. There were people arguing that the server market is suit even with only 1 dominant player, considering Intel is doomed to compete with outdated Intel CPUs and can't find the money for to slow down its replace cycle. They disagree, as it is obvious that the lack of competition is causing Intel to rate its top Xeon EP fairly somewhat better. within the midrange, there is no pressure to present an awful lot more suitable efficiency per dollar: a small increase is what they get. The recently launched Xeon E5 v3 is barely 15% faster on the same fee than the Xeon E5 v2. So they might basically want to see some match competition.

    sure, economies of scale is among the explanations that Intel was competent to overtake the RISC competition. besides the fact that children, simply accounting Intel's success back at the conclusion of previous century to being the player with the highest unit earnings is short sighted. seem at the table below, which describes the situation again in late 1995:

    seller CPU SPECint95 SPECfp95 Intel Pentium pro two hundredeight.2 6.8 digitalAlpha 21164 333 MHz 9.8 13.four MIPS (SGI) R8000 90 MHz 5.five12 solar extremely I 167 MHz 6.6 9.4 HP PA7200-RISC 120MHz 6.4 9.1

    There are three issues remember to word. First, except the Alpha 21164, Intel managed to outperform each RISC competitor available with their first server chip in integer performance. Intel managed this by brilliant execution and imaginitive micro-architecture aspects (such because the 256KB SRAM + core MCM kit and out-of-order micro-ops returned-conclusion). Intel also had a system expertise lead and used 350nm whereas the relaxation of the competitors changed into nevertheless stuck at 500nm.

    second, Intel turned into fortunate that the true performer – Alpha – had the bottom marketshare, utility base, and advertising power. Third, the server and notebook market was divided between the RISC avid gamers. application building changed into very fragmented among the many RISC systems.

    So in a nutshell, there have been several the reason why Intel succeeded at breaking into the server market anyway their better user base within the desktop world:

  • concentrated investments in a vertical construction line and impressive execution, and in consequence the premiere process technology on this planet
  • The efficiency and know-how leader was not the strongest player in the market
  • The market become fragmented, so divide and triumph over changed into a lot less complicated
  • presently, the ARM SoC challengers would not have those benefits. as far as they comprehend, Intel's system remains the most advanced manner know-how on earth. Samsung is likely shut but for the time being their subsequent generation process is not attainable to the Intel rivals.

    at this time, Intel dominates - or more accurately owns - the server market. every possible piece of costly utility runs on Intel, which is a extremely diverse circumstance from again in the RISC world of the nineties, the place many pieces of important software best ran on certain RISC CPUs. today, the server market is anything else but fragmented. That makes the scale competencies of the ARM rivals a very weak argument. Intel's person base – the transforming into server market and declining laptop market – is huge adequate to sustain heavy R&D investments for a long time, contrary to the RISC providers in the nineties which had to share a extremely profitable but once again fragmented market.

    when you are now not convinced, just imagine the Alpha 21164 became the dominant RISC Server CPU, with 90-ninety five% server market share. just think about that instead of getting some server functions running best on SPARC or on HP PA-RISC, that every server utility ran on Alpha. Now mix this with the proven fact that home windows on Alpha became purchasable. it's relatively glaring that it will be were a whole lot harder for Intel to damage into the server and pc market had this been the case.

    So simply as a result of ARM SoCs are offered in the billions doesn't suggest they will immediately overtake Intel server CPUs. Intel beat the RISC gamers because the market was fragmented, and because none of them had been executing as well as Intel. For ARM options to in fact benefit traction, they need to do much more than comfortably compete in a few area of interest markets, as Calxeda has shown.

    The previous web page might provide the influence that they do not deliver the ARM gamers a chance towards mighty Intel. That is not the case, but they agree with that the wrong arguments are sometimes used. Intel's success become also end result of the the big amount of home windows laptop clients that were enthusiastic about the usage of their home windows potential in knowledgeable environment. The mixture of home windows NT and the success of the Pentium professional become very potent.

    ARM additionally has such a "Trojan software horse" and it's referred to as the Linux based mostly cloud. We're not saying the rest new when they are saying that cloud functions have in fact taken off and that the cyber web of issues will make cloud functions much more essential. those cloud services have been making a tsunami of innovation and are in accordance with open supply initiatives equivalent to Hadoop, Spark, Openstack, MongoDB, Cassandra, first rate old Apache, and hundreds of others. That software stack is ported or being ported to the ARM software ecosystem.

    however you probably knew that. Let's make it more concrete. just ages in the past they visited the fb hardware lab. Being a server hardware fanatic, they felt like a toddler in a huge toy keep. Let me introduce you to facebook's Open Vault, a part of the the Open Compute venture:

    ... is a simple and reasonably-priced storage solution with a modular I/O topology that’s developed for the Open Rack. The Open Vault offers high disk densities, holding 30 drives in a 2U chassis, and may operate with well-nigh any host server.

    Mat Corddry, director of hardware of engineering showed us the hardware:

    the first incarnation of the "honey badger" micro server is in accordance with Avoton. but nothing is stopping facebook from the use of an ARM micro server in their Open Vault machines if it presents the identical capabilities and is more affordable and/or lower power. As low priced storage is extremely crucial within the "massive statistics" age, this is just one of the opportunities that the "smaller" ARM server SoCs have. but it additionally makes another point: they must beat the Intel SoCs that are already general and used.

    The RISC vs. CISC dialogue is rarely ending. It started as quickly because the first RISC CPUs entered the market within the mid eighties. simply six years in the past, Anand reported that AMD's CTO, Fred Weber was claiming:

    Fred mentioned that the overhead of preserving x86 compatibility changed into negligible, on the time round 10% of the die became the x86 decoder and that percent would best shrink over time.

    just like Intel today, AMD claimed that the overhead of the advanced x86 ISA was dwindling speedy because the transistor budget grew exponentially with Moore's legislations. however the issue to remember is that excessive rating managers will all the time make statements that fit their current approach and vision. lots of the time there is some certainty in it, but the subtleties and nuances of the story are the primary victims in press releases and statements.

    Now in 2014, it's decent to position an end to all this dialogue: the ISA is not a video game changer, nevertheless it matters! AMD is now in an excellent position to choose as it will enhance x86 and ARM CPUs through the equal crew, lead by the identical CPU architecture veteran. They listened carefully to what Jim Keller, the top of the AMD CPU architect team, needed to say within the 4th minute of this YouTube video:

    "The large fundamental component is that ARMv8 ISA has greater registers (32), a three operand ISA, and spends less transistors on decoding and dealing with the complexities of x86. That permits us to spend more transistors on efficiency... ARM gives us some inherent architectural effectivity."

    that you could debate until you drop, but there is not any denying that the x86 ISA requires more pipeline tiers and thus transistors to decode than any decent RISC ISA. As x86 guidelines are variable length, fetching instructions is less efficient and requires more transistors. The guide cache is additionally greater as you should shop pre-decode information. The again-conclusion might contend with RISC-like micro-ops however because the fruits need to adhere to rules of the x86 ISA, accordingly transistors are spent on exception managing and condition codes.

    or not it's proper that the percent of transistors spent on decoding has dwindled over the years. however the number of cores has multiplied greatly. as a result, the x86 tax isn't imaginary.

    while they suppose that the ARMv8 ISA is basically a aggressive capabilities for the ARM server SoCs, the hardware accelerators are a huge mystery: they have no concept how significant the performance or vigour potential is in real utility. It should be would becould very well be mind-blowing or it might possibly be simply yet another "offload works best within the rare case the place all these circumstances are met". nevertheless, it's exciting to see how the ARM server SoC has numerous integrated accelerators.

    Most of them are the commonplace IPSec, TCP offloading engines, and Cryptographic accelerators. It can be unique to look if the ARM ecosystem can offer extra really good gadgets that can actually outperform the general Intel offerings.

    One IP block that obtained my attention become the the Regex accelerators of Cavium. commonplace expression accelerators are really expert in pattern attention and might be very effective for search engines like google, community protection, and facts analytics. That seems exactly what they need within the current killer apps. but the devil is in the particulars: it'll want application help, and preferably on a wide scale.

    of 1 component they are certain: the "more affordable, smaller, greater quantity alternative historically wins" is a really weak argument to make when claiming that ARM SoCs will overtake Intel in the server market. it's hard to make all the puzzle pieces come together: efficiency, power, quantity, and software. Low costs and quantity are not adequate. they might love to see some real competition in the server market, but Intel is plenty more advantageous located nowadays to fend off assaults than the RISC players were again in the 90s.

    The latest ARM server SoCs are much more potent than Calxeda's ECX-a thousand, but they don't face a hopelessly out of date Atom S1200 anymore. The Atom C2000 is a major step forward and the Xeon E3 has persisted to evolve in such a means that even eight of the best ARM cores can't convey more uncooked integer processing energy than a quad-core E3 with SMT. in the meantime, the Xeon-D will present the entire merits of the excessive performance "Broadwell" structure, the flexibleness of Intel's turbo enhance, Intel's striking system technology, and the highly integrated Atom C2000 SoC in one very competitive equipment.

    the primary – albeit very rough – efficiency records suggests that the server ARMada isn't in a position (yet?) to take on the most fulfilling Intel Xeons in a vast range of server applications, at least in terms of efficiency. despite the fact, the ARM challengers do have a chance. despite the huge number of Intel SKUs, Intel's market segmentation is reasonably crude and assumes that every one shoppers can readily be categorized into three (might be 4) enormous businesses: For low budgets, get the low latitude Xeon E3 (e.g. E3-1220 v3). Pay somewhat greater and you get Hyper-Threading and better clock speeds (E3-1240 v3). Pay slightly extra and you get yet another velocity bump. Pay lots greater and you get 4 reminiscence channels. they are going to throw in more cores and a larger cache as a bonus (Xeon E5).

    What if I even have a badly scaling HPC utility (low core count number) that wants lots of memory bandwidth? There isn't any Xeon E3 with quad channel. What if i want huge quantities of memory however average processing power? The Xeon E3 only supports 32GB. What if my utility needs lots of cores and bandwidth but doesn't benefit from huge and gradual LLC caches? There isn't any Xeon E5 for that; i will handiest select one of the vital expensive E5s. And these examples don't seem to be invented; applications like these exist in the genuine world and don't seem to be exotic exceptions. What if my software benefits from a definite hardware accelerator? purchase a few 100k of SoCs and they are going to talk. Intel's market segmentation is based mostly on the idea that every need (I/O, caches, reminiscence bandwidth, reminiscence ability) is proportional to processing vigour.

    The ARM based mostly challengers have the skills to serve these "ordinary" but tremendously big markets stronger. The can charge to increase new SoCs is lower and ARMv8 has the inherent RISC expertise of spending fewer transistors on ISA complexity. This lowers the Intel abilities of technique know-how management.

    Cavium has a clear focus and goals the dimensions-out, telecom, and storage markets. they are very curious how the primary chip which is specialized for "scale-out" functions will function. It has been a long time given that they now have considered this type of specialized SoC and it's crystal clear that efficiency will fluctuate a lot depending on the software. Their first impact is that the chip may be ultimate operating a lot of community intensive virtual machines on appropriate of a hypervisor, comparable to Xen or KVM.

    AppliedMicro's X-Gene appears to goal a a lot wider latitude of purposes, attacking the Intel Xeon E3 and the quickest Atom C2000. The hardware accelerators and quad-channel memory should still supply it an side in some server purposes whereas staying close adequate in others. lots will depend upon how quickly the X-Gene 2 is obtainable in true servers. The X-Gene 2 "ShadowCat" is already up and running, so they now have excessive hopes.

    Broadcom looks to have an analogous strategy. Broadcom is late but is a market leader with deep pockets and an surprising list of valued clientele. The same is true for Qualcomm. but they wants specs and never just broad and vague statements earlier than they commit greater phrases to the server plans of Qualcomm.

    AMD's Opteron A1100 is really making a bet on undercutting Intel's low-conclusion Xeons in cost and lines. every little thing about it screams "time to market, low cost however proven low power design". The more ambitious AMD ARM SoCs will come later, despite the fact, because the current A1100 is lacking an important function: a link to the liberty cloth. The network cloth is a critical function as OEMs can then construct a low power, high performance networked micro server cluster. It became the strongest element of the Calxeda based mostly servers as it saved energy per node low, offered very low latency community, and diminished the investments in expensive network apparatus (Cisco et al.). AMD is a well known brand with the commercial enterprise folks and has a lot of exciting server/HPC IP.

    ultimate however no longer least, many agencies within the IT world including HP, fb and Google are looking to see greater competitors within the server market. So all ARM licensees can count number on some goodwill to make it ensue.

    We from their aspect were Getting ready as smartly. they have developed a couple of new benchmarks to look at various this new breed of servers. challenging numbers say greater than just phrases, however you are going to must look forward to part two of this series for those.

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  • Art Conservator in private practice since 2001.
  • Art Conservator for the Rosco Group in Dorval, QC (specialists in disaster recovery and restoration) 2001.
  • Art Conservator for the The Vermont Museums and Galleries Alliance,The Old Stone House Museum and Crystal Lake Falls, 2000.
  • Historical Association, Brownington and Barton, VT, U.S.A., The Greenwood Centre for Living History, Hudson, QC, 1999.
  • Art Conservation Intern at the Nationalmuseet, Brede Conservation Centre, Lyngby, Denmark, 1998-1999.
  • Art Conservation Intern at the National Archives of Canada-The Gatineau Preservation Centre, Gatineau, QC, 1998.
  • Art Conservation Intern at the The National Gallery of Canada, Ottawa, ON, 1994.
  • Studied at the Université de Paris I-Panthéon-Sorbonne, Paris, FR (L'Etude des Sciences et Techniques de la Conservation et la Restauration des Biens Culturels 1993-1999.
  • Concordia University in Montreal, QC Bachelor of Fine Arts: History of Art and Studio Arts (1992); Diploma of Environmental Design from the The Ontario College of Art, Toronto, ON (1989)
  • I have taught at the Saidye Bronfman Center for the Arts, in Montreal (the salted paper technique), the Japanese Paper Store in Montreal photograph album making; and given workshops in preventative conservation at the Greenwood for Living History in Hudson, Quebec.

For a complete resume please contact us.